The present disclosure relates to a clock data recovery (CDR) circuit having a function of reproducing a clock signal from data having a clock signal embedded in a data row, and relates to, for example, a technique effective in a case of application to a data input interface circuit using a CDR circuit.
In recent years, there has been progress in the speed-up of an interface between a transmission device and a receiving device due to high definition of a display used in a smartphone or a tablet terminal. Hitherto, a source synchronous system has been widely used in which a transmission device sends out a clock together with data, and a receiving device fetches data using this clock. However, in the source synchronous system, a skew between a clock and data is obstructive to speeding up, and thus a so-called embedded clock system in which a clock is embedded in data and is transmitted has recently begun to be used.
Reception using an embedded clock system uses a CDR (Clock Data Recovery) circuit having a function of separating a clock from data, and the performance of this CDR circuit has a lot of influence on the performance of a device having the circuit incorporated therein and the entire application system thereof.
There is JP-A-2012-44446 as an example of a document in which a CDR circuit is described. In JP-A-2012-44446, a clock data recovery circuit that generates and outputs a clock signal for extracting data from a data signal transmitted in a serial manner includes a frequency-locked loop for locking the clock signal to a desired frequency using a predetermined reference clock signal, and a phase-locked loop for phase-synchronizing the clock signal with the data signal in the frequency locked state of the clock signal. Frequency comparison of a reference clock signal with the generated clock signal is performed during an operation of the frequency-locked loop, a clock signal frequency having a frequency according to the comparison result is locked, and the phase of the frequency-locked clock signal is synchronized with the phase of input data by bringing the phase-locked loop into operation.
As in JP-A-2012-44446, in the case that the reference clock is provided, and frequency lock is performed using the reference clock, the setting of an oscillation circuit is fixed after frequency lock in the case of unnecessary continuous reception for a long period of time. However, in the case of unnecessary continuous reception for a long period of time, a locked state may continue to be maintained by the reference clock even after frequency lock.
The CDR may not be provided with the reference clock. In this case, a clock signal is initially self-oscillated at the receiving device side, the adjustment of the clock signal is performed on the frequency of input data by detecting the edge of input data, and a frequency is locked. After the frequency lock is, the setting of the oscillation circuit is fixed. After the oscillation frequency is locked, a timing error of a minute phase is corrected using the phase-locked loop.